This invention relates to a multi-CPU device for industrial applications, and more particularly to a multi-CPU device including a master CPU block mounted therein with a general purpose operating system (OS) and a slave CPU block mounted therein with a realtime OS.
A conventional multi-CPU device is constructed in such a manner as shown in FIGS. 5 and 6 by way of example. More specifically, a multi-CPU device generally designated at reference numeral 30 in FIG. 5 is provided therein with a power supply 18. The power supply 18 is constructed so as to convert an AC current fed thereto from an external feed circuit 21 through a UPS 22 into a DC current required and output it therefrom. The power supply 18 is connected to both a master-side structure 1 and a slave-side structure 19.
The master-side structure 1 is adapted to be operated by an operator and includes a master CPU block 2 mounted therein with a general purpose OS suitable for a user interface. The master CPU block 2 includes a CPU 3, a ROM 4 and a RAM 5 and has a storage means 6, an input unit 7 such as a key board, a mouse or the like, and a monitor 8 connected thereto.
Also, the master-side structure 1 includes a bus 9 connected to the master CPU block 2. The bus 9 has a common memory 20 connected to one end thereof, so that a signal may be transmitted between the master CPU block 2 and the common memory 20 through the common memory 20.
The slave-side structure 19 is adapted to control an equipment to be controlled (hereinafter referred to as "controlled equipment") 50 such as a production apparatus or the like and includes a slave CPU block 12. The slave CPU block 12 is mounted therein with a realtime OS having realtime characteristics suitable for a control system. Also, the slave CPU block 12 includes a CPU 13, a ROM 14 and a RAM 15 and has a bus 11 connected thereto. The bus 11 is connected to a control function blocks 16 and 17.
The bus 11 thus arranged is connected at one end thereof to the common memory 20 described above. The common memory 20 functions as a memory which permits the master CPU block 2 of the master-side structure 1 and the slave CPU block 12 of the slave-side structure 19 to be accessed to each other through the buses 9 and 11 through the common memory 20. Such construction permits a signal to be transmitted through the common memory 20 between the master CPU block 2 of the master-side structure 1 and the slave CPU block 12 of the slave-side structure 19.
The control function blocks 16 and 17 described above each function as a contact input and output section, an analog/digital converter (hereinafter referred to as "A/D converter"), a digital-analog converter (hereinafter referred to as "D/A converter") and the like. The control function blocks 16 and 17 are connected directly to the controlled equipment 50. The control function blocks 16 and 17 control the controlled equipment 50 depending on a signal outputted from the slave CPU block 12.
In FIGS. 5 and 6, arrows of a double line each indicate a current feed wiring and other arrows each indicate a signal line.
Now, the manner of control of the controlled equipment 50 by the conventional multi-CPU device 30 will be described.
First, when the multi-CPU device 30 is activated, a control program stored in the storage means 6 of the master-side structure 1 is down-loaded through the master CPU block 2, bus 9, common memory 20 and bus 11 to the RAM 15 of the slave CPU block 12 according to an activation program previously stored in the ROM 14. The control program thus down-loaded functions to control both function and operation timings of the control function blocks 16 and 17. Such down-loading of the control program to the RAM 15 permits the CPU 13 to control the control function blocks 16 and 17 according to the control program thus down-loaded.
In the conventional multi-CPU device 30 thus constructed, the control function block 16 functions as a D/A converter, to thereby output an analog signal to the controlled equipment 50. Thus, the controlled equipment 50 is operated depending on the signal, so that a result of the operation is output in the form of an analog signal to the control function block 17. In this case, the control function block 17 acts as an A/D converter, to thereby fetch the analog signal fed from the controlled equipment 50, resulting in converting it into a digital signal, followed by returning of the digital signal to the CPU 13. The CPU 13 functions to control a timing at which the control function block 16 output the analog signal, a timing at which the control function block 17 fetches the analog signal from the controlled equipment 50 and a timing at which the control function block 17 outputs the digital signal to the CPU 13.
Now, construction of a plurality of the thus-constructed multi-CPU devices 30 into a production line or the like will be described with reference to FIG. 6. The current feed circuit 21 is connected to the UPS 22, which is then connected to a plurality of the multi-CPU devices 30. The multi-CPU devices 30 each function to control the controlled equipment 50 connected thereto.
The UPS 22 includes a battery (not shown) and a service interruption sensing circuit (not shown). The UPS 22 functions to feed an AC current fed from the current feed circuit 21 therethrough to the power supply 18 of each of the multi-CPU devices 30 without any action on the AC current. Also, the UPS 22, when feed of the AC current from the current feed circuit 21 is interrupted due to service interruption or the like, functions to convert a DC current fed from the battery into an AC current and feed the AC current to the power supply 18 arranged in each of the multi-CPU devices 30.
Such arrangement of the UPS 22 between the current feed circuit 21 and each of the multi-CPU devices 30 is for the purpose of preventing system-down of the multi-CPU device 30 when feed of a current to the multi-CPU device 30 is abruptly interrupted due to service interruption or the like. In particular, the general purpose OS mounted in the master CPU block 2 of each of the multi-CPU devices 30 possibly causes loss or vanishment of data unless it is shut down according to a predetermined procedure. In order to eliminate such a problem, the conventional multi-CPU device is so constructed that the battery of the UPS 22 continues to feed a current during at least a period of time for which the shutdown is executed, resulting in ensuring that the shutdown is normally attained while ensuring satisfactory storage of the data.
To this end, an operator must normally shut down the multi-CPU device 30 prior to exhaustion of a battery current of the UPS 22, when service interruption occurs. Although an increase in capacity of the battery would increase a period of time for which the battery can feed a current, this renders the battery equipment large-sized and complicated, leading to an increase in both a space for the battery and a manufacturing cost of the battery. Thus, an increase in capacity of the battery should be limited to a reduced level. Thus, an operator is still required to execute shutdown of the multi-CPU device as soon as service interruption occurs.
In particular, in a line wherein a plurality of multi-CPU devices 30 are arranged as shown in FIG. 6, an operator must manually shut down all of the master CPU blocks 2 of the individual multi-CPU devices 30 within a period of time for which the battery feeds a current. This causes operation by the operator to be highly troublesome and often leads to a failure in shutdown of the master CPU blocks 2.
In view of the foregoing, a system is proposed which is adapted to automatically shut down the general purpose OSs by means of the UPS. The system proposed is constructed so as to connect the multi-CPU device and UPS to each other by communications. Thus, the UPS is required to be provided with a program for shutdown corresponding to each of the general purpose OSs connected to the UPS. Also, construction of a system which permits automatic shutdown of the general purpose OSs between the UPS and the general purpose OSs which have no relationship to each other in connection with a software requires much time and costs a great deal.
Also, the system proposed renders operation of the general purpose OS unstable and, in the worst case, causes it to be often locked. Such locking of the general purpose OS leads to stoppage of the multi-CPU device 30 and therefore stoppage of the controlled equipment 50 connected thereto. However, an operator fails to perceive locking of the general purpose OS unless he operates a key board or the like.
When the operator is late in perceiving the locking, the controlled equipment 50 is kept interrupted. Such interruption or stoppage of the controlled equipment 50 for a long period of time causes a great loss when it is a manufacturing equipment.